URL https://opencores.org/ocsvn/xucpu/xucpu/trunk

Subversion Repositories xucpu

[/] [xucpu/] [trunk] - Rev 16

Rev	Log message	Author	Age	Path
16	Re-write of memory in function of initial array memory blocks.	lcdsgmtr	3187d 00h	/xucpu/trunk
15	Unification of all RAM parts into one interface.	lcdsgmtr	3187d 00h	/xucpu/trunk
14	Simple implementation project.	lcdsgmtr	3318d 22h	/xucpu/trunk
13	Updated smallest Xilinx configuration.	lcdsgmtr	3318d 22h	/xucpu/trunk
12	Update Xilinx configurations.	lcdsgmtr	3318d 22h	/xucpu/trunk
11	Successful run of the simulation. Correct results.	lcdsgmtr	3319d 00h	/xucpu/trunk
10	Correct build with GHDL.	lcdsgmtr	3319d 00h	/xucpu/trunk
9	This makes sure that this GHDL configuration analyses correctly.	lcdsgmtr	3319d 00h	/xucpu/trunk
8	Rebuilding the configuration to build the first system using GHDL.	lcdsgmtr	3319d 23h	/xucpu/trunk
7	Moved package for initialising memory also to src.	lcdsgmtr	3319d 23h	/xucpu/trunk
6	Removed some unnecessary files and directories. Moved other files to new directories.	lcdsgmtr	3319d 23h	/xucpu/trunk
5	Re-organisation of repository.	lcdsgmtr	3321d 00h	/xucpu/trunk
4	Added directories for guiding implementation using Xilinx ISE and GHDL.	lcdsgmtr	3356d 00h	/xucpu/trunk
3	Added Makefile for GHDL.	lcdsgmtr	3440d 22h	/xucpu/trunk
2	First checkin to make sure that the project does not get stale.	lcdsgmtr	3443d 01h	/xucpu/trunk
1	The project and the structure was created	root	3467d 07h	/xucpu/trunk