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[/] [xucpu/] [trunk] - Rev 21

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21 Since all BRAM is unified in one component, this testbench is not necessary
anymore.		 lcdsgmtr 3329d 12h /xucpu/trunk
20 Update RAM package to allow for 15-bit address.
Update test bench to use address width parameter.		 lcdsgmtr 3329d 12h /xucpu/trunk
19 Makefile for building memory block testbench. lcdsgmtr 3329d 12h /xucpu/trunk
18 Ignore work files from GHDL. lcdsgmtr 3329d 12h /xucpu/trunk
17 Moving the generic block ram component piece by piece to a better
implementation.		 lcdsgmtr 3329d 12h /xucpu/trunk
16 Re-write of memory in function of initial array memory blocks. lcdsgmtr 3329d 12h /xucpu/trunk
15 Unification of all RAM parts into one interface. lcdsgmtr 3329d 12h /xucpu/trunk
14 Simple implementation project. lcdsgmtr 3461d 10h /xucpu/trunk
13 Updated smallest Xilinx configuration. lcdsgmtr 3461d 10h /xucpu/trunk
12 Update Xilinx configurations. lcdsgmtr 3461d 10h /xucpu/trunk
11 Successful run of the simulation. Correct results. lcdsgmtr 3461d 12h /xucpu/trunk
10 Correct build with GHDL. lcdsgmtr 3461d 12h /xucpu/trunk
9 This makes sure that this GHDL configuration analyses correctly. lcdsgmtr 3461d 12h /xucpu/trunk
8 Rebuilding the configuration to build the first system using GHDL. lcdsgmtr 3462d 11h /xucpu/trunk
7 Moved package for initialising memory also to src. lcdsgmtr 3462d 11h /xucpu/trunk
6 Removed some unnecessary files and directories.
Moved other files to new directories.		 lcdsgmtr 3462d 11h /xucpu/trunk
5 Re-organisation of repository. lcdsgmtr 3463d 12h /xucpu/trunk
4 Added directories for guiding implementation using Xilinx ISE and GHDL. lcdsgmtr 3498d 12h /xucpu/trunk
3 Added Makefile for GHDL. lcdsgmtr 3583d 10h /xucpu/trunk
2 First checkin to make sure that the project does not get stale. lcdsgmtr 3585d 13h /xucpu/trunk

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