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[/] [xulalx25soc/] [trunk/] [bench/] [cpp/] [busmaster_tb.cpp] - Rev 106

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106 Minor, inconsequential changes. dgisselq 2877d 18h /xulalx25soc/trunk/bench/cpp/busmaster_tb.cpp
96 Now accepts an SD-Card backing file, so that SD-Card reads *and* writes can be
tested.		 dgisselq 2900d 22h /xulalx25soc/trunk/bench/cpp/busmaster_tb.cpp
75 Added simulation capability for the SD-Card, as well as debugging output for the
DMA. (The SD-Card debug may not be fully featured, yet, but it has gotten me
to where I can talk to the card.)		 dgisselq 2906d 18h /xulalx25soc/trunk/bench/cpp/busmaster_tb.cpp
47 Fixes the "NAN" clocks/second output, as well as making input timing come closer
to a realistic timing. (I actually don't know what timing the JTAG port is
providing, but ... the new timer is closer.)		 dgisselq 2984d 22h /xulalx25soc/trunk/bench/cpp/busmaster_tb.cpp
37 These fixes were necessary to get the SDRAM into a working simulation
capability. It is finally what it was supposed to be: cycle accurate. Sadly,
to do this, I did need to make a subtle change to rtl/wbsdram.v. (I was having
a problem with external input clocking in Verilator. This fixes it--but its
a Verilator only change--to rtl/wbsdram.v that is.)		 dgisselq 2992d 22h /xulalx25soc/trunk/bench/cpp/busmaster_tb.cpp
31 A bug fix, although one that rearranges the bus. The first four I/O locations
have been adjusted. The new locations are reflected in wishbone.html. In
addition, the PWM and UART devices no longer create bus errors when accessed.
Finally, this version uses a `define XULA25 to determine whether or not to build
for the XuLA2-LX9 or the XuLA2-LX25. If defined, it will build for the
XuLA2-LX25. If not, for the XuLA2-LX9. The ideal location for this define
would be to place it into your Xilinx configuration, should you wish to build
for the LX25.		 dgisselq 2996d 21h /xulalx25soc/trunk/bench/cpp/busmaster_tb.cpp
4 Here's an initial, albeit incomplete, build. dgisselq 3067d 17h /xulalx25soc/trunk/bench/cpp/busmaster_tb.cpp

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