| Rev |
Log message |
Author |
Age |
Path |
| 118 |
Lots of changes. The biggest are to the CPU: MPYxHI instructions are now
verified to be working, ILLegal instructions stop at the right location,
the STEP bit no longer self-clears, etc. Other changes cleaned up the
internal documentation and removed parameters that should only have local
scope from the global parameter list. The NEW_INSTRUCTION_SET was also
removed from the CPU, since ... it's been new for too long to really be new
anymore. |
dgisselq |
2825d 23h |
/xulalx25soc/trunk/bench/cpp |
| 117 |
Updates, to include new README and bench/cpp/Makefile that doesnt depend upon
a static VERILATOR_ROOT location. |
dgisselq |
2850d 15h |
/xulalx25soc/trunk/bench/cpp |
| 116 |
Fixes a compiler warning about signed versus unsigned comparison, by forcing
the comparison to be signed. |
dgisselq |
2935d 01h |
/xulalx25soc/trunk/bench/cpp |
| 115 |
Made the SDCard support dependent upon a XULA25 macro, which is defined at the
top of the file. Remove the XULA25 macro definition, and this will build
assuming a XULA9 configuration. |
dgisselq |
2943d 16h |
/xulalx25soc/trunk/bench/cpp |
| 113 |
Lots of updates, mostly focused on getting the XuLA board and CPU able to pass
a comprehensive test suite. At this point, everything passes and logic usage
is down even. Among the few changes includes the "break" bit in the uCC
register, used to indicate a switch to supervisor mode occurred as a result
of a user break, and the ability for the supervisor to clear the instruction
cache. |
dgisselq |
2943d 16h |
/xulalx25soc/trunk/bench/cpp |
| 112 |
Provides a simulated UART capability to the busmaster_tb simulation. |
dgisselq |
2945d 21h |
/xulalx25soc/trunk/bench/cpp |
| 106 |
Minor, inconsequential changes. |
dgisselq |
2952d 10h |
/xulalx25soc/trunk/bench/cpp |
| 96 |
Now accepts an SD-Card backing file, so that SD-Card reads *and* writes can be
tested. |
dgisselq |
2975d 15h |
/xulalx25soc/trunk/bench/cpp |
| 95 |
Added write capability to the SD-SPI simulator. |
dgisselq |
2975d 15h |
/xulalx25soc/trunk/bench/cpp |
| 94 |
Fixes a bug which had caused the device to die artificially and early, just
simply because the program connecting to the simulator shut its pipe down before
getting our last message. We now ignore this signal and continue. |
dgisselq |
2975d 15h |
/xulalx25soc/trunk/bench/cpp |
| 75 |
Added simulation capability for the SD-Card, as well as debugging output for the
DMA. (The SD-Card debug may not be fully featured, yet, but it has gotten me
to where I can talk to the card.) |
dgisselq |
2981d 11h |
/xulalx25soc/trunk/bench/cpp |
| 47 |
Fixes the "NAN" clocks/second output, as well as making input timing come closer
to a realistic timing. (I actually don't know what timing the JTAG port is
providing, but ... the new timer is closer.) |
dgisselq |
3059d 15h |
/xulalx25soc/trunk/bench/cpp |
| 37 |
These fixes were necessary to get the SDRAM into a working simulation
capability. It is finally what it was supposed to be: cycle accurate. Sadly,
to do this, I did need to make a subtle change to rtl/wbsdram.v. (I was having
a problem with external input clocking in Verilator. This fixes it--but its
a Verilator only change--to rtl/wbsdram.v that is.) |
dgisselq |
3067d 15h |
/xulalx25soc/trunk/bench/cpp |
| 31 |
A bug fix, although one that rearranges the bus. The first four I/O locations
have been adjusted. The new locations are reflected in wishbone.html. In
addition, the PWM and UART devices no longer create bus errors when accessed.
Finally, this version uses a `define XULA25 to determine whether or not to build
for the XuLA2-LX9 or the XuLA2-LX25. If defined, it will build for the
XuLA2-LX25. If not, for the XuLA2-LX9. The ideal location for this define
would be to place it into your Xilinx configuration, should you wish to build
for the LX25. |
dgisselq |
3071d 14h |
/xulalx25soc/trunk/bench/cpp |
| 4 |
Here's an initial, albeit incomplete, build. |
dgisselq |
3142d 09h |
/xulalx25soc/trunk/bench/cpp |
