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[/] [xulalx25soc/] [trunk/] [rtl/] [cpu/] [zipcpu.v] - Rev 118

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118 Lots of changes. The biggest are to the CPU: MPYxHI instructions are now
verified to be working, ILLegal instructions stop at the right location,
the STEP bit no longer self-clears, etc. Other changes cleaned up the
internal documentation and removed parameters that should only have local
scope from the global parameter list. The NEW_INSTRUCTION_SET was also
removed from the CPU, since ... it's been new for too long to really be new
anymore.		 dgisselq 2753d 18h /xulalx25soc/trunk/rtl/cpu/zipcpu.v
117 Updates, to include new README and bench/cpp/Makefile that doesnt depend upon
a static VERILATOR_ROOT location.		 dgisselq 2778d 09h /xulalx25soc/trunk/rtl/cpu/zipcpu.v
113 Lots of updates, mostly focused on getting the XuLA board and CPU able to pass
a comprehensive test suite. At this point, everything passes and logic usage
is down even. Among the few changes includes the "break" bit in the uCC
register, used to indicate a switch to supervisor mode occurred as a result
of a user break, and the ability for the supervisor to clear the instruction
cache.		 dgisselq 2871d 11h /xulalx25soc/trunk/rtl/cpu/zipcpu.v
98 Updated copyright notices for the new year, to reflect that changes have been
made in 2016.		 dgisselq 2880d 06h /xulalx25soc/trunk/rtl/cpu/zipcpu.v
89 Bug fixes, following the adf_ce logic combining ALU/DIVIDE/FPU pipeline logic
into one register, this fixes that logic so that instructions without their
condition fulfilled are still "executed" and marked as done.		 dgisselq 2903d 10h /xulalx25soc/trunk/rtl/cpu/zipcpu.v
73 Simplified logic. dgisselq 2909d 06h /xulalx25soc/trunk/rtl/cpu/zipcpu.v
52 This brings the XuLA2-LX25 SoC up to speed with the rest of the ZipCPU, and
prepares it for the 32x32 bit multiply instruction set change.		 dgisselq 2957d 07h /xulalx25soc/trunk/rtl/cpu/zipcpu.v
51 Lots of bug fixes. The ugliest were in the prefetch cache, where instructions
from one cache line were being issued as valid in another. Other fixes include
pipeline fixes so that LOD (Rx),Rx; LOD(Rx),Rx works, and more. Finally, the
decode was adjusted so that brev no longer affects the flags.		 dgisselq 2967d 05h /xulalx25soc/trunk/rtl/cpu/zipcpu.v
50 Updates to fix some broken early branching code, both in idecode and pfcache. dgisselq 2976d 08h /xulalx25soc/trunk/rtl/cpu/zipcpu.v
46 This is a bug fix release--fixing the bug that kept dumpsdram.cpp/wbsdram.v
from working when long pipelined reads were interrupted by the necessity of
a pair of refresh cycles.		 dgisselq 2987d 10h /xulalx25soc/trunk/rtl/cpu/zipcpu.v
26 Some bug fixes, and the long jump early branching integration. dgisselq 3000d 09h /xulalx25soc/trunk/rtl/cpu/zipcpu.v
21 Files, not links, to replace what were once broken links in this project. dgisselq 3061d 18h /xulalx25soc/trunk/rtl/cpu/zipcpu.v

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