URL https://opencores.org/ocsvn/xulalx25soc/xulalx25soc/trunk

Subversion Repositories xulalx25soc

[/] [xulalx25soc/] [trunk/] [rtl/] [wbsdram.v] - Rev 42

Rev	Log message	Author	Age	Path
39	An attempt at a bugfix. We'll see if this works any better downstream.	dgisselq	3163d 18h	/xulalx25soc/trunk/rtl/wbsdram.v
37	These fixes were necessary to get the SDRAM into a working simulation capability. It is finally what it was supposed to be: cycle accurate. Sadly, to do this, I did need to make a subtle change to rtl/wbsdram.v. (I was having a problem with external input clocking in Verilator. This fixes it--but its a Verilator only change--to rtl/wbsdram.v that is.)	dgisselq	3164d 15h	/xulalx25soc/trunk/rtl/wbsdram.v
2	A very first, albeit incomplete, build.	dgisselq	3239d 10h	/xulalx25soc/trunk/rtl/wbsdram.v