OpenCores
URL https://opencores.org/ocsvn/xulalx25soc/xulalx25soc/trunk

Subversion Repositories xulalx25soc

[/] [xulalx25soc/] [trunk/] [sw/] [regdefs.h] - Rev 116

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
77 Adds register names and values for the SD card interface. dgisselq 3075d 16h /xulalx25soc/trunk/sw/regdefs.h
33 Oops -- the audio was wired audio first then the interrupt controller, not
the other way around. This adjusts regdefs to match what's on the chip.		 dgisselq 3165d 18h /xulalx25soc/trunk/sw/regdefs.h
31 A bug fix, although one that rearranges the bus. The first four I/O locations
have been adjusted. The new locations are reflected in wishbone.html. In
addition, the PWM and UART devices no longer create bus errors when accessed.
Finally, this version uses a `define XULA25 to determine whether or not to build
for the XuLA2-LX9 or the XuLA2-LX25. If defined, it will build for the
XuLA2-LX25. If not, for the XuLA2-LX9. The ideal location for this define
would be to place it into your Xilinx configuration, should you wish to build
for the LX25.		 dgisselq 3165d 19h /xulalx25soc/trunk/sw/regdefs.h
29 This adds a vastly updated and superious ziprun capability to the repository.
ziprun now accepts ELF program files *only*, reads them, and places them onto
the board. This includes the ability, within the ELF file, of specifying
whether or not the data is sent to block ram, SD ram, or Flash, as well as
the ability of specifying the initial address. (Of course, that's a one time
thing--to always have the same initial address, set the address in
rtl/busmaster.v)		 dgisselq 3166d 15h /xulalx25soc/trunk/sw/regdefs.h
24 Added the #define necessary to enable (and clear) SCOPE interrupts. dgisselq 3172d 18h /xulalx25soc/trunk/sw/regdefs.h
17 Some basic updates, to include adding in a missing file (zipstate). Most of
these updates include making sure that the XuLA2 device can be accessed via
the USB. (Prior versions accessed the FPGA via serial port or network ...)		 dgisselq 3231d 19h /xulalx25soc/trunk/sw/regdefs.h
11 Getting software up and running on the board for the first time. (Not there
yet, but I think these items have now proven themselves.)		 dgisselq 3233d 18h /xulalx25soc/trunk/sw/regdefs.h
5 Initial software version, in support of the project. At this point, they are
provided with no guarantees that they work. (They did use to work--on an older
build, but I haven't been able to verify that they work with this newer build
yet.)		 dgisselq 3236d 14h /xulalx25soc/trunk/sw/regdefs.h

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.