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[/] [xulalx25soc/] [trunk/] [sw] - Rev 105

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105 Mostly cosmetic changes. The Makefile now builds a couple more programs,
the documentation is better, etc.
dgisselq 3022d 12h /xulalx25soc/trunk/sw
104 Updates to the flash driver drawn from the S6SoC project. dgisselq 3022d 12h /xulalx25soc/trunk/sw
103 Added a SDSPI scope, and defined which of the four scopes it points to.
(It uses the configuration scopes position, if the configuration scope isn't
defined.)
dgisselq 3022d 12h /xulalx25soc/trunk/sw
93 Oops -- missed adjusting the copyright. dgisselq 3045d 16h /xulalx25soc/trunk/sw
92 Fixes the problem whereby the master counters show when the user counters should
be showing and vice versa. Now the master counters show by default, together
with their correct labels. User counters are still available by pressing
'u' in the debugger, and the master counter display may be returned to by
pressing 'm' in the debugger.
dgisselq 3045d 16h /xulalx25soc/trunk/sw
91 Fixes bugs associated with an overflow of write acknowledgements in the
receiver. This helps keep our accesses aligned.
dgisselq 3045d 16h /xulalx25soc/trunk/sw
78 Comments out the line that caused a compiler warning--setting an unused
variable. Code should be better as a result.
dgisselq 3051d 12h /xulalx25soc/trunk/sw
77 Adds register names and values for the SD card interface. dgisselq 3051d 12h /xulalx25soc/trunk/sw
76 Now tries to avoid reading from the stack if the stack addresses are already
known to be bad. That way, the debugger tries to preserve any bus error address
already on the buserr device.
dgisselq 3051d 12h /xulalx25soc/trunk/sw
53 Added a touch of error checking. dgisselq 3099d 13h /xulalx25soc/trunk/sw
49 Added some documentation to make the read and write calls easier to understand. dgisselq 3127d 15h /xulalx25soc/trunk/sw
46 This is a bug fix release--fixing the bug that kept dumpsdram.cpp/wbsdram.v
from working when long pipelined reads were interrupted by the necessity of
a pair of refresh cycles.
dgisselq 3129d 16h /xulalx25soc/trunk/sw
42 Minor changes. dgisselq 3133d 12h /xulalx25soc/trunk/sw
41 Bug fix. This was preventing dumpsdram from accurately reading back what
had been written to the RAM earlier.
dgisselq 3133d 12h /xulalx25soc/trunk/sw
40 This adds to dumpsdram the capability to run over a port, such as with
busmaster_tb.
dgisselq 3134d 23h /xulalx25soc/trunk/sw
38 Updated to remove the build dependence upon ZipCPU. dgisselq 3136d 22h /xulalx25soc/trunk/sw
33 Oops -- the audio was wired audio first then the interrupt controller, not
the other way around. This adjusts regdefs to match what's on the chip.
dgisselq 3141d 15h /xulalx25soc/trunk/sw
31 A bug fix, although one that rearranges the bus. The first four I/O locations
have been adjusted. The new locations are reflected in wishbone.html. In
addition, the PWM and UART devices no longer create bus errors when accessed.
Finally, this version uses a `define XULA25 to determine whether or not to build
for the XuLA2-LX9 or the XuLA2-LX25. If defined, it will build for the
XuLA2-LX25. If not, for the XuLA2-LX9. The ideal location for this define
would be to place it into your Xilinx configuration, should you wish to build
for the LX25.
dgisselq 3141d 15h /xulalx25soc/trunk/sw
30 Bug fixes. In particular, this fixes a segmentation violation. dgisselq 3141d 19h /xulalx25soc/trunk/sw
29 This adds a vastly updated and superious ziprun capability to the repository.
ziprun now accepts ELF program files *only*, reads them, and places them onto
the board. This includes the ability, within the ELF file, of specifying
whether or not the data is sent to block ram, SD ram, or Flash, as well as
the ability of specifying the initial address. (Of course, that's a one time
thing--to always have the same initial address, set the address in
rtl/busmaster.v)
dgisselq 3142d 11h /xulalx25soc/trunk/sw

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