OpenCores
URL https://opencores.org/ocsvn/yifive/yifive/trunk

Subversion Repositories yifive

[/] [yifive/] [trunk/] [caravel_yifive/] [verilog/] [rtl] - Rev 22

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
22 test bench update dinesha 1150d 21h /yifive/trunk/caravel_yifive/verilog/rtl
21 Simulation clean up and wishbone interconnect added dinesha 1150d 21h /yifive/trunk/caravel_yifive/verilog/rtl
20 digital core added into svn dinesha 1155d 12h /yifive/trunk/caravel_yifive/verilog/rtl
19 sdram control added dinesha 1155d 16h /yifive/trunk/caravel_yifive/verilog/rtl
18 spi master added dinesha 1155d 16h /yifive/trunk/caravel_yifive/verilog/rtl
17 syntacore_scr1 directory removal dinesha 1156d 11h /yifive/trunk/caravel_yifive/verilog/rtl
16 syntacore_scr1 directory removal dinesha 1156d 11h /yifive/trunk/caravel_yifive/verilog/rtl
15 syntacore_scr1 directory removal dinesha 1156d 11h /yifive/trunk/caravel_yifive/verilog/rtl
14 syntacore_scr1 directory removal dinesha 1156d 11h /yifive/trunk/caravel_yifive/verilog/rtl
13 syntacore_scr1 directory removal dinesha 1156d 11h /yifive/trunk/caravel_yifive/verilog/rtl
12 syntacore_scr1 directory removal dinesha 1156d 11h /yifive/trunk/caravel_yifive/verilog/rtl
11 syntacore directory update dinesha 1156d 11h /yifive/trunk/caravel_yifive/verilog/rtl
10 syntacore interface change to wishbone dinesha 1156d 12h /yifive/trunk/caravel_yifive/verilog/rtl
8 synthesis script update dinesha 1157d 12h /yifive/trunk/caravel_yifive/verilog/rtl
7 synth script clean up dinesha 1157d 12h /yifive/trunk/caravel_yifive/verilog/rtl
6 first yosys synthesisizable rtl dinesha 1157d 13h /yifive/trunk/caravel_yifive/verilog/rtl
5 Webstone interface update dinesha 1157d 17h /yifive/trunk/caravel_yifive/verilog/rtl
4 Removed Git igonore command file dinesha 1157d 18h /yifive/trunk/caravel_yifive/verilog/rtl
3 1. Initial version of westbone interface files copied from turbo8051 open core project
2. Initial version of RISCV Open core project copied from Syntacore SCR1 package		 dinesha 1157d 18h /yifive/trunk/caravel_yifive/verilog/rtl
2 Initial version of efabless caravel user project dinesha 1157d 18h /yifive/trunk/caravel_yifive/verilog/rtl

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.