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[/] [yifive/] [trunk/] [caravel_yifive/] [verilog] - Rev 22

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Rev Log message Author Age Path
22 test bench update dinesha 1210d 19h /yifive/trunk/caravel_yifive/verilog
21 Simulation clean up and wishbone interconnect added dinesha 1210d 19h /yifive/trunk/caravel_yifive/verilog
20 digital core added into svn dinesha 1215d 11h /yifive/trunk/caravel_yifive/verilog
19 sdram control added dinesha 1215d 15h /yifive/trunk/caravel_yifive/verilog
18 spi master added dinesha 1215d 15h /yifive/trunk/caravel_yifive/verilog
17 syntacore_scr1 directory removal dinesha 1216d 10h /yifive/trunk/caravel_yifive/verilog
16 syntacore_scr1 directory removal dinesha 1216d 10h /yifive/trunk/caravel_yifive/verilog
15 syntacore_scr1 directory removal dinesha 1216d 10h /yifive/trunk/caravel_yifive/verilog
14 syntacore_scr1 directory removal dinesha 1216d 10h /yifive/trunk/caravel_yifive/verilog
13 syntacore_scr1 directory removal dinesha 1216d 10h /yifive/trunk/caravel_yifive/verilog
12 syntacore_scr1 directory removal dinesha 1216d 10h /yifive/trunk/caravel_yifive/verilog
11 syntacore directory update dinesha 1216d 10h /yifive/trunk/caravel_yifive/verilog
10 syntacore interface change to wishbone dinesha 1216d 10h /yifive/trunk/caravel_yifive/verilog
8 synthesis script update dinesha 1217d 11h /yifive/trunk/caravel_yifive/verilog
7 synth script clean up dinesha 1217d 11h /yifive/trunk/caravel_yifive/verilog
6 first yosys synthesisizable rtl dinesha 1217d 11h /yifive/trunk/caravel_yifive/verilog
5 Webstone interface update dinesha 1217d 16h /yifive/trunk/caravel_yifive/verilog
4 Removed Git igonore command file dinesha 1217d 16h /yifive/trunk/caravel_yifive/verilog
3 1. Initial version of westbone interface files copied from turbo8051 open core project
2. Initial version of RISCV Open core project copied from Syntacore SCR1 package		 dinesha 1217d 16h /yifive/trunk/caravel_yifive/verilog
2 Initial version of efabless caravel user project dinesha 1217d 17h /yifive/trunk/caravel_yifive/verilog

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