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[/] [zipcpu/] [trunk/] [rtl/] [zipbones.v] - Rev 209

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209 8b bytes, + formal verification throughout + dcache dgisselq 2058d 15h /zipcpu/trunk/rtl/zipbones.v
201 RTL files for the 8-bit capable ZipCPU. dgisselq 2798d 00h /zipcpu/trunk/rtl/zipbones.v
183 Cleaned up the system so that !CYC implies !STB as well. dgisselq 2972d 22h /zipcpu/trunk/rtl/zipbones.v
105 Fixed some nasty early branching bugs. Adjusted the Makefile to declare that
cpudefs.h was automatically generated from cpudefs.v, and made sure that
zipbones included the cpudefs.v so it could get the DEBUG_SCOPE define.
In addition, the test.S was updated to test long jumps, the early branching
bug we found, and all three early branching instructions: ADD #x,PC, LOC(PC),PC,
and LDI #x,PC.		 dgisselq 3163d 03h /zipcpu/trunk/rtl/zipbones.v
91 Minor updates. dgisselq 3203d 20h /zipcpu/trunk/rtl/zipbones.v
69 This implements the "new Instruction Set" architecture for the Zip CPU. It's
a massive change set, that touches just about everything but probably not
enough of everything. Please see the spec.pdf for a description of this
new architecture.		 dgisselq 3241d 02h /zipcpu/trunk/rtl/zipbones.v
66 Adjusted the support for the DEBUG_SCOPE within these so that it can be
compiled in, or not, based upon an external build configuration file: cpudefs.v.
That allows me to make that file project specific, while the rest of the CPU
is shared among all projects.		 dgisselq 3302d 02h /zipcpu/trunk/rtl/zipbones.v
56 Here's a bit of work in progress for getting the Zip CPU working on a XuLA2
board. Many changes include: the existence of a cpudefs.v file to control
what "options" are included in the ZipCPU build. This allows build control
to be separated from the project directory (one build for a XuLA2 board,
another for a Basys-3 development board). Other changes have made things
perhaps harder to read, but they get rid of warnings from XST.

A big change was the addition of the (* ram_style="distributed" *) comment
for the register set. This was necessary to keep XST from inferring a block
RAM and breaking the logic that was supposed to take place between a register
read and when it was used.		 dgisselq 3312d 05h /zipcpu/trunk/rtl/zipbones.v
48 Files added/updated to get Dhrystone benchmark to work. Several fixes
to the CPU in the process, 'cause it wasn't working. Stall-less ALU
ops now work better, to include grabbing the memory result as it comes out
of the memory unit and placing it straight into either ALU or memory unit
for the next instruction.		 dgisselq 3321d 21h /zipcpu/trunk/rtl/zipbones.v
38 A couple of quick updates:

- The Zip CPU now supports pipelined memory access at one clock per
instruction (assuming all the instructions are in the cache)
- There is now a 'zipbones' module to build a Zip System without peripherals.
Any peripherals would then need to be external to the CPU.
- Some bug fixes.

Documentation changes coming shortly.		 dgisselq 3325d 02h /zipcpu/trunk/rtl/zipbones.v

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