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Rev Log message Author Age Path
26 New directory structure. root 5681d 02h /
25 XOR bug fixed jsauermann 6739d 09h /
24 no message jsauermann 6900d 07h /
23 Fixed problem with wishbone wait-states jsauermann 7040d 06h /
22 This commit was manufactured by cvs2svn to create tag 'Rev_XLNX_7'. 7040d 12h /
21 Changes for Xilinx Proj. Nav. 7.1.02i jsauermann 7040d 12h /
20 This commit was manufactured by cvs2svn to create tag 'Rev_XLNX_5'. 7236d 08h /
19 FPGA Pin desription added. jsauermann 7236d 08h /
18 Assert ENABLE_INT and DISABLE_INT only in M1.
Thanks to Riccardo Cerulli-Irelly.
Requires a fix in rtos.c as well
jsauermann 7537d 07h /
17 Assert ENABLE_INT and DISABLE_INT only in M1.
Thanks to Riccardo Cerulli-Irelly.
Requires a fix in rtos.c as well
jsauermann 7537d 07h /
16 Enable interrupts at start of each task.
This fix is required after a change in opcode_decoder.vhd.
jsauermann 7537d 08h /
15 sample ucf file jsauermann 7576d 11h /
14 no message jsauermann 7584d 12h /
13 bug in print_unsigned() fixed.
Now done as in rtos.c
jsauermann 7627d 05h /
12 Todo removed jsauermann 7656d 03h /
11 First Version jsauermann 7656d 03h /
10 Set top of stack of idle task to end of internal memory rather
than end of external memory (causing incorrect display of
100 % CPU load).
jsauermann 7656d 05h /
9 Made cpu_engine WISHBONE compliant.
(Somebody please validate it).
jsauermann 7656d 05h /
8 Initialization of compound auto variables added (was TODO) jsauermann 7663d 08h /
7 Handle auto variable declarations in compound statements properly jsauermann 7664d 07h /

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