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Rev Log message Author Age Path
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 4700d 05h /
355 Import Julius Baxter's verilator hints from ORPSoC olof 4700d 06h /
354 Whitespace cleanup olof 4700d 07h /
353 Inherit fixes for bit width of constants from ORPSoC olof 4702d 08h /
352 Removed delayed assignments from rtl code olof 4706d 14h /
351 Turn defines into parameters in eth_cop olof 4715d 04h /
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 4715d 04h /
349 Make all parameters configurable from top level olof 4716d 05h /
348 Added option to dump VCD files olof 4717d 04h /
347 Added information about running with Icarus Verilog olof 4717d 05h /
346 Updated project location olof 4717d 07h /
345 Temporarily disable failing tests olof 4717d 08h /
344 bit 9 in phy control register is self clearing olof 4723d 10h /
343 Address miss should not be asserted on short frames olof 4727d 06h /
342 Added cast to avoid inequality when comparing different data types olof 4727d 06h /
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 4727d 07h /
340 Don't fail if log dir already exists olof 4728d 04h /
339 Added basic support for Icarus Verilog olof 4729d 03h /
338 root 5521d 09h /
337 root 5577d 11h /

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