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[/] - Rev 4

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Rev Log message Author Age Path
4 Added a howto for getting started. ayersg 4512d 13h /
3 Made whitespace consistent in all Verilog files. ayersg 4514d 16h /
2 Initial release ayersg 4515d 02h /
1 The project and the structure was created root 4516d 03h /

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