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Rev Log message Author Age Path
38 Reduced processing latency of Huffman encoding mikel262 5701d 22h /
37 Replaced VHDL Header RAM with Verilog, initialized via readmemh from hex file. mikel262 5706d 02h /
36 Fixed RLE ZRL bug. Added Chrominance Huffman tables. Fixed num encoded bytes bug. mikel262 5707d 22h /
35 Added check for image width in testbench. mikel262 5708d 10h /
34 Moved Quantizer to separate pipeline stage to balance processing chain load. mikel262 5708d 18h /
33 mikel262 5709d 03h /
32 mikel262 5709d 22h /
31 Specification update, minor area improvements in BUF_FIFO. mikel262 5712d 23h /
30 mikel262 5713d 11h /
29 mikel262 5713d 19h /
28 BU_FIFO SUB_RAM is now monolithic single block used by all SubFIFO - effect much less memory block usage. mikel262 5713d 19h /
27 mikel262 5716d 08h /
26 mikel262 5716d 08h /
25 moved from branch to trunk mikel262 5716d 09h /
24 mikel262 5716d 09h /
23 mikel262 5717d 19h /
22 Changed divider to use reciprocal lookup table. Improved Huffman processing time. BUF_FIFO almost full signal modified. mikel262 5718d 20h /
21 Huffman.vhd processing latency shortened. mikel262 5719d 19h /
20 Added compressed JPEG output file from testbench mikel262 5719d 20h /
19 Timing improved in MDCT and in Huffman mikel262 5719d 22h /

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