OpenCores
URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] - Rev 496

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
496 ORPSoC ml501 updates - increased frequency, updated documentation julius 5013d 03h /
495 ORPSoC adding more accessor functions to Micron SDRAM model. julius 5013d 03h /
494 Change to ensure handles ctrl-C correctly with empty line. jeremybennett 5023d 21h /
493 ORPSoC VPI JTAG interface, hopefully fix 64-bit machine compile issues. julius 5026d 05h /
492 ORPSoC VPI interface for modelsim and documentation update julius 5027d 03h /
491 ORPSoC or1200_monitor update. julius 5027d 14h /
490 Updates to fix spurious test failures and register scheduling. jeremybennett 5031d 20h /
489 ORPSoC sw cleanup. Remove warnings. julius 5037d 02h /
488 ORPSoC OR1200 driver - tick timer exception handler reverted to generic - cpu tick function hook used as default in handler table. OR1200 timer demo sw for board added. julius 5037d 03h /
487 ORPSoC main software makefile update julius 5040d 01h /
486 ORPSoC updates, mainly software, i2c driver julius 5040d 01h /
485 ORPSoC updates - or1200 monitor now has separate defines file, ethmac updates to fifos and wishbone IF, board.h changes for UART (may propegate to other drivers with multiple cores, we'll see), crt0.S for or1200 now zeros all registers on reset, adding own ethernet tests for ML501 julius 5044d 05h /
484 Changes to make r12 call-saved and to bring wchar tests in line. jeremybennett 5045d 04h /
483 Updated with new opcodes to generate random numbers and to identify us as Or1ksim. jeremybennett 5047d 06h /
482 Don't hardcode tool versions in help text olof 5048d 18h /
481 OR1200 Update. RTL and spec. julius 5060d 12h /
480 ORPSoC updates - ml501 project cleanups, DDR2 cache bug fixes. julius 5061d 10h /
479 ORPSoC update to ml501 board port. Memory controller caching fixed up, does multiple lines of cache and Wishbone bursting. julius 5062d 09h /
478 ORPSoC update - ml501 or1200 cache configuration set to maximum, some cleanups. julius 5064d 01h /
477 ORPSoC update - Added ability to enable OR1200 caches up to 32KB, which requires line size of 32bytes and 8-beat Wishbone bursts.
Changed cache sizes of both instruction and data cache of reference design to 4kB each.		 julius 5064d 09h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.