URL https://opencores.org/ocsvn/sha256_hash_core/sha256_hash_core/trunk

Subversion Repositories sha256_hash_core

[/] - Rev 10

Rev	Log message	Author	Age	Path
10	Optimized control logic; Reduced one clock cycle for full last blocks, eliminated sch_ld redundant logic. Improved error detection logic, eliminating the bytes error register. Updated testbench with write violations and full block corner case tests.	jdoin	3007d 10h	/
9	Optimized control logic; Changed 'ack' semantics to 'data write'. Changed error logic to detect invalid data writes.	jdoin	3022d 07h	/
8	Streamlined VHDL code to eliminate wire and combinational "initialization", changed all 'X' to 'U' on input signals, consisted comments.	jdoin	3092d 12h	/
7	Delete intermediate files from repository. All commits are done after a Project/Cleanup.	jdoin	3094d 22h	/
6	Added Sim_test_1.png and Sim_test_8.png simulation pictures. Changed testbench for faster data input. Changed License text on all files. Consolidated file header info.	jdoin	3094d 22h	/
5	Reduced images sizes.	jdoin	3096d 01h	/
4	Reduced block diagrams image sizes.	jdoin	3096d 01h	/
3	Added GV_SHA256 block logic schematics.	jdoin	3096d 04h	/
2	SHA256 RTL code simulated and verified, to all NIST verification vectors. Pre-par synthesis show 74MHz clock rate, with no pipelining.	jdoin	3096d 06h	/
1	The project and the structure was created	root	3100d 05h	/