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Rev Log message Author Age Path
108 removed unneeded files jt_eaton 4769d 07h /
107 added designCfg files to all modules jt_eaton 4769d 10h /
106 checked in orp_soc project step 2 jt_eaton 4775d 03h /
105 moved or1200_monitor from testbench to dut jt_eaton 4777d 23h /
104 fixed search in preprocessor script
added initial orp_soc project		 jt_eaton 4780d 00h /
103 added user guide
resynced to local repository		 jt_eaton 4800d 01h /
102 all ip-xact files now readable by kactus2 jt_eaton 4861d 20h /
101 Added new designs for minsoc release candidate
convert tool set to parse proper ip-xact

THIS WILL BREAK ALL THE OLD DESIGNS UNTIL I FIX THEIR IP_XACT		 jt_eaton 4862d 22h /
100 created workspace prroject=fpga_mrisc for single compile
general cleanup		 jt_eaton 4875d 05h /
99 moved all projects into /projects/opencores.org
added build_register
added fizzim		 jt_eaton 4917d 22h /
98 removed unneeded sim jt_eaton 4954d 02h /
97 changed sim run directory to icarus
added ise directory into syn
added _tb testbench file to all sims		 jt_eaton 4954d 03h /
96 hierConnections now create ports jt_eaton 5027d 23h /
95 added first cut at busdefs
added clock reset enable pads and jtag_rpc		 jt_eaton 5036d 21h /
94 socgen now supports both sim and syn views
now allow each xml file to set its destination		 jt_eaton 5063d 22h /
93 build scripts now support model views
linting and coverage starting to work again		 jt_eaton 5076d 11h /
92 all testbenchs now built from /sim/xml files
bench /models now in Testbench		 jt_eaton 5081d 12h /
91 fixed all sims, coverage not working jt_eaton 5089d 06h /
90 now build all testbenches from ip-xact files and list as testbench in design.soc jt_eaton 5089d 22h /
89 removed unneeded debug directories jt_eaton 5111d 07h /

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