URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] - Rev 114

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Rev	Log message	Author	Age	Path
114	moved or1200 connectivity out of verilog and into ip-xact added or1200_boot block removed force of 00 on lowest iwb_addr bits	jt_eaton	4608d 17h	/
113	started refactoring or1200	jt_eaton	4614d 09h	/
112	added more test sims removed unneeded files	jt_eaton	4623d 22h	/
111	split or1200 out into seperate test suite	jt_eaton	4625d 16h	/
110	split out more ip-xact components added sw sources	jt_eaton	4637d 14h	/
109	removed unused file	jt_eaton	4640d 14h	/
108	removed unneeded files	jt_eaton	4641d 20h	/
107	added designCfg files to all modules	jt_eaton	4641d 23h	/
106	checked in orp_soc project step 2	jt_eaton	4647d 16h	/
105	moved or1200_monitor from testbench to dut	jt_eaton	4650d 12h	/
104	fixed search in preprocessor script added initial orp_soc project	jt_eaton	4652d 13h	/
103	added user guide resynced to local repository	jt_eaton	4672d 13h	/
102	all ip-xact files now readable by kactus2	jt_eaton	4734d 09h	/
101	Added new designs for minsoc release candidate convert tool set to parse proper ip-xact THIS WILL BREAK ALL THE OLD DESIGNS UNTIL I FIX THEIR IP_XACT	jt_eaton	4735d 10h	/
100	created workspace prroject=fpga_mrisc for single compile general cleanup	jt_eaton	4747d 18h	/
99	moved all projects into /projects/opencores.org added build_register added fizzim	jt_eaton	4790d 11h	/
98	removed unneeded sim	jt_eaton	4826d 14h	/
97	changed sim run directory to icarus added ise directory into syn added _tb testbench file to all sims	jt_eaton	4826d 16h	/
96	hierConnections now create ports	jt_eaton	4900d 12h	/
95	added first cut at busdefs added clock reset enable pads and jtag_rpc	jt_eaton	4909d 10h	/

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Subversion Repositories socgen

[/] - Rev 114

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