URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] - Rev 120

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Rev	Log message	Author	Age	Path
120	clean up componentGenerators names and directories sim + lint now synthesis TestBench	jt_eaton	4628d 20h	/
119	moved copyright files into /verilog changed cde copyright to apache from gplv3 split out tools into separate subdirectories changed design.xml files to socgen: namespace	jt_eaton	4663d 15h	/
118	optimized gen_verilog added padring support added configuration support added jtag sims added accellera candidate bus defs	jt_eaton	4699d 00h	/
117	added yellow pages tools	jt_eaton	4726d 19h	/
116	added build_header now use build_register for all spr components resynced or1200 code back to use orbuild toolchain	jt_eaton	4761d 16h	/
115	split or1200_cpu up into all ip-xact components removed dead files	jt_eaton	4805d 20h	/
114	moved or1200 connectivity out of verilog and into ip-xact added or1200_boot block removed force of 00 on lowest iwb_addr bits	jt_eaton	4817d 20h	/
113	started refactoring or1200	jt_eaton	4823d 12h	/
112	added more test sims removed unneeded files	jt_eaton	4833d 01h	/
111	split or1200 out into seperate test suite	jt_eaton	4834d 20h	/
110	split out more ip-xact components added sw sources	jt_eaton	4846d 17h	/
109	removed unused file	jt_eaton	4849d 17h	/
108	removed unneeded files	jt_eaton	4850d 23h	/
107	added designCfg files to all modules	jt_eaton	4851d 02h	/
106	checked in orp_soc project step 2	jt_eaton	4856d 19h	/
105	moved or1200_monitor from testbench to dut	jt_eaton	4859d 15h	/
104	fixed search in preprocessor script added initial orp_soc project	jt_eaton	4861d 16h	/
103	added user guide resynced to local repository	jt_eaton	4881d 16h	/
102	all ip-xact files now readable by kactus2	jt_eaton	4943d 12h	/
101	Added new designs for minsoc release candidate convert tool set to parse proper ip-xact THIS WILL BREAK ALL THE OLD DESIGNS UNTIL I FIX THEIR IP_XACT	jt_eaton	4944d 13h	/

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[/] - Rev 120

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