URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] - Rev 46

Rev	Log message	Author	Age	Path
46	removed hard coded component names from design files define file is always defines.v top level is always top.v	jt_eaton	5228d 19h	/
45	added 6502 sims/software and synth	jt_eaton	5235d 15h	/
44	added new parts and sw for 6502	jt_eaton	5235d 18h	/
43	complete rework of states and sequencer added interrupts moved prog space and vectors to F space	jt_eaton	5245d 16h	/
42	removed old versions that used prog as C space	jt_eaton	5245d 16h	/
41	added kim-1 design and program now support Nexys2 sdram	jt_eaton	5263d 17h	/
40	removed test for deleted block	jt_eaton	5263d 17h	/
39	added io_probe to sims added boot rom into 6502 added T6502_control	jt_eaton	5272d 05h	/
38	fsm level removed	jt_eaton	5272d 06h	/
37	continued to clean up inst decodes to alu and move datapath out of sequencer removed latched alu_result, now uses raw	jt_eaton	5281d 13h	/
36	split out alu_ctrl block split out alu decode signals	jt_eaton	5282d 06h	/
35	added T6502 doc	jt_eaton	5283d 10h	/
34	removed BCD mode from T6502 started to convert design to use datapath logic for alu	jt_eaton	5288d 13h	/
33	removed unused block	jt_eaton	5288d 13h	/
32	renamed to T6502_state_fsm	jt_eaton	5288d 19h	/
31	split T6502_fsm out into smaller blocks	jt_eaton	5289d 09h	/
30	split out fsm code into seperate modules fixed bugs so that prog_test passes	jt_eaton	5291d 18h	/
29	removed old files	jt_eaton	5294d 17h	/
28	added T6502 processor added vga_char_ctrl	jt_eaton	5294d 17h	/
27	added uart and ps2 host and models added more documentation	jt_eaton	5316d 08h	/