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[/] - Rev 90

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Rev Log message Author Age Path
90 now build all testbenches from ip-xact files and list as testbench in design.soc jt_eaton 5088d 10h /
89 removed unneeded debug directories jt_eaton 5109d 19h /
88 added xml files for test benches
added gEDA sym sch starter templates
jt_eaton 5109d 19h /
87 removed prebuilt geda schematics and symbols jt_eaton 5120d 12h /
86 split out all fpgas into families
added fpga pad_ring level
jt_eaton 5128d 09h /
85 moved all synthesis into fpgas lib
fixed memory leak in recursive routines
jt_eaton 5135d 08h /
84 removed unneeded files jt_eaton 5185d 13h /
83 added design.soc files
xml files now 99% 1685 complient
jt_eaton 5185d 17h /
82 renmamed cde_synchronizers to cde_sync
added hierarchial dependency search
converted more xmp to follow ip-xact
jt_eaton 5200d 11h /
81 morphing xml files to use 1685
removed log directories
jt_eaton 5221d 18h /
80 now generate all sims and syns param and filelists for xml jt_eaton 5251d 09h /
79 removed unsupported code jt_eaton 5257d 13h /
78 removed unsupported fpga jt_eaton 5257d 13h /
77 now generate syn and cov Makefiles
leave log and out files in sim/run directory
jt_eaton 5257d 14h /
76 added wave.save files
now generate sims Makefile and params.sim
leave sim log and vcd files in sim/run/directory
jt_eaton 5259d 19h /
75 added linting using verilator jt_eaton 5263d 11h /
74 split out sw Makefile into projects /bin
split out _cpu into seperate component
jt_eaton 5268d 17h /
73 removed dup png files jt_eaton 5276d 16h /
72 split T6502 into components
moved io_module into seperate project
removed liblists
direct loads filelists for sims and coverage
add hier type into xml files to generate verilog
jt_eaton 5276d 18h /
71 ignore anything in work jt_eaton 5283d 11h /

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