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Rev Log message Author Age Path
93 build scripts now support model views
linting and coverage starting to work again		 jt_eaton 5089d 23h /
92 all testbenchs now built from /sim/xml files
bench /models now in Testbench		 jt_eaton 5095d 00h /
91 fixed all sims, coverage not working jt_eaton 5102d 18h /
90 now build all testbenches from ip-xact files and list as testbench in design.soc jt_eaton 5103d 10h /
89 removed unneeded debug directories jt_eaton 5124d 19h /
88 added xml files for test benches
added gEDA sym sch starter templates		 jt_eaton 5124d 19h /
87 removed prebuilt geda schematics and symbols jt_eaton 5135d 12h /
86 split out all fpgas into families
added fpga pad_ring level		 jt_eaton 5143d 09h /
85 moved all synthesis into fpgas lib
fixed memory leak in recursive routines		 jt_eaton 5150d 08h /
84 removed unneeded files jt_eaton 5200d 13h /
83 added design.soc files
xml files now 99% 1685 complient		 jt_eaton 5200d 17h /
82 renmamed cde_synchronizers to cde_sync
added hierarchial dependency search
converted more xmp to follow ip-xact		 jt_eaton 5215d 11h /
81 morphing xml files to use 1685
removed log directories		 jt_eaton 5236d 17h /
80 now generate all sims and syns param and filelists for xml jt_eaton 5266d 09h /
79 removed unsupported code jt_eaton 5272d 13h /
78 removed unsupported fpga jt_eaton 5272d 13h /
77 now generate syn and cov Makefiles
leave log and out files in sim/run directory		 jt_eaton 5272d 14h /
76 added wave.save files
now generate sims Makefile and params.sim
leave sim log and vcd files in sim/run/directory		 jt_eaton 5274d 19h /
75 added linting using verilator jt_eaton 5278d 11h /
74 split out sw Makefile into projects /bin
split out _cpu into seperate component		 jt_eaton 5283d 16h /

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