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[/] - Rev 97

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Rev Log message Author Age Path
97 changed sim run directory to icarus
added ise directory into syn
added _tb testbench file to all sims
jt_eaton 4910d 14h /
96 hierConnections now create ports jt_eaton 4984d 10h /
95 added first cut at busdefs
added clock reset enable pads and jtag_rpc
jt_eaton 4993d 08h /
94 socgen now supports both sim and syn views
now allow each xml file to set its destination
jt_eaton 5020d 09h /
93 build scripts now support model views
linting and coverage starting to work again
jt_eaton 5032d 21h /
92 all testbenchs now built from /sim/xml files
bench /models now in Testbench
jt_eaton 5037d 22h /
91 fixed all sims, coverage not working jt_eaton 5045d 17h /
90 now build all testbenches from ip-xact files and list as testbench in design.soc jt_eaton 5046d 09h /
89 removed unneeded debug directories jt_eaton 5067d 18h /
88 added xml files for test benches
added gEDA sym sch starter templates
jt_eaton 5067d 18h /
87 removed prebuilt geda schematics and symbols jt_eaton 5078d 10h /
86 split out all fpgas into families
added fpga pad_ring level
jt_eaton 5086d 07h /
85 moved all synthesis into fpgas lib
fixed memory leak in recursive routines
jt_eaton 5093d 06h /
84 removed unneeded files jt_eaton 5143d 12h /
83 added design.soc files
xml files now 99% 1685 complient
jt_eaton 5143d 16h /
82 renmamed cde_synchronizers to cde_sync
added hierarchial dependency search
converted more xmp to follow ip-xact
jt_eaton 5158d 10h /
81 morphing xml files to use 1685
removed log directories
jt_eaton 5179d 16h /
80 now generate all sims and syns param and filelists for xml jt_eaton 5209d 07h /
79 removed unsupported code jt_eaton 5215d 12h /
78 removed unsupported fpga jt_eaton 5215d 12h /

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