URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

[/] - Rev 264

Rev	Log message	Author	Age	Path
264	Final synthesis results. Gates, sdc, tcl, conf, etc.	creep	5462d 11h	/
263	Added the final reports from synthesis without a VCD	creep	5462d 11h	/
262	Final synthesis script.	creep	5462d 11h	/
261	Added a better clock gating scheme with enable sharing	creep	5462d 14h	/
260	removing useless files	creep	5465d 08h	/
259	sync	creep	5465d 08h	/
258	Fixed the input parametric testing logic, removed a pad.	creep	5465d 08h	/
257	Modified script for DFT	creep	5487d 11h	/
256	fp files	creep	5487d 11h	/
255	Changed the PADS verilog description to minimize violations	creep	5487d 11h	/
254	Fixed a latch in the design	creep	5487d 11h	/
253	Changed the rw_mem signal name in the hierarchy	creep	5510d 12h	/
252	Added a stubs file for the pads.	creep	5510d 12h	/
251	Added the io wrapper	creep	5510d 15h	/
250	Synthesis script changed	creep	5510d 15h	/
249	Renamed the synthesis script	creep	5511d 11h	/
248	Added a low power synthesis script	creep	5516d 10h	/
247	Added the cpu mapped verilog	creep	5516d 10h	/
246	Added some older files plus the first syn script	creep	5517d 14h	/
245	Added a few dirs for the synthesis	creep	5517d 15h	/