URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] - Rev 112

Rev	Log message	Author	Age	Path
112	change timers to meet timing specifications (add divider with 12)	simont	7790d 21h	/
111	Remove instruction cache and wb_interface	simont	7791d 12h	/
110	change adr_i and adr_o length.	simont	7791d 12h	/
109	add `include "oc8051_defines.v"	simont	7791d 12h	/
108	fix some bugs, use oc8051_cache_ram.	simont	7791d 12h	/
107	Include instruction cache.	simont	7791d 12h	/
106	generic_dpram used	simont	7792d 15h	/
105	generic_dpram used	simont	7792d 15h	/
104	use generic_dpram	simont	7792d 15h	/
103	rename signals	simont	7792d 16h	/
102	raname signals.	simont	7792d 16h	/
101	initial inport	simont	7792d 19h	/
100	use \	simont	7792d 20h	/
99	change directory structure	simont	7792d 20h	/
98	move to rtl/verilog	simont	7792d 20h	/
97	initial inport	simont	7792d 20h	/
96	initial import	simont	7792d 20h	/
95	updating...	simont	7792d 20h	/
94	fix bug.	simont	7792d 20h	/
93	OC8051_XILINX_RAM added	simont	7792d 20h	/