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URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

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Rev Log message Author Age Path
114 remove t2mod register simont 7766d 19h /
113 signal prsc_ow added. simont 7766d 19h /
112 change timers to meet timing specifications (add divider with 12) simont 7766d 19h /
111 Remove instruction cache and wb_interface simont 7767d 10h /
110 change adr_i and adr_o length. simont 7767d 10h /
109 add `include "oc8051_defines.v" simont 7767d 10h /
108 fix some bugs, use oc8051_cache_ram. simont 7767d 10h /
107 Include instruction cache. simont 7767d 10h /
106 generic_dpram used simont 7768d 13h /
105 generic_dpram used simont 7768d 13h /
104 use generic_dpram simont 7768d 13h /
103 rename signals simont 7768d 14h /
102 raname signals. simont 7768d 14h /
101 initial inport simont 7768d 17h /
100 use \ simont 7768d 17h /
99 change directory structure simont 7768d 17h /
98 move to rtl/verilog simont 7768d 18h /
97 initial inport simont 7768d 18h /
96 initial import simont 7768d 18h /
95 updating... simont 7768d 18h /

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