OpenCores
URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] - Rev 132

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
132 change branch instruction execution (reduse needed clock periods). simont 7763d 00h /
131 prepare programs for new timing. simont 7763d 00h /
130 prepared programs for new timing. simont 7763d 00h /
129 updated... simont 7763d 00h /
128 chance idat_ir to 24 bit wide simont 7772d 07h /
127 fix bug (cyc_o and stb_o) simont 7772d 07h /
126 define OC8051_XILINX_RAMB added simont 7772d 07h /
125 update, add prescaler, rclk, tclk. simont 7772d 07h /
124 add support for external rom from xilinx ramb4 simont 7772d 07h /
123 fiz bug iv pcs operation. simont 7774d 02h /
122 deifne OC8051_ROM added simont 7777d 07h /
121 Change pc add value from 23'h to 16'h simont 7777d 07h /
120 defines for pherypherals added simont 7778d 04h /
119 remove signal sbuf_txd [12:11] simont 7778d 08h /
118 change wr_sft to 2 bit wire. simont 7779d 01h /
117 Register oc8051_sfr dato output, add signal wait_data. simont 7779d 01h /
116 change sfr's interface. simont 7781d 02h /
115 change uart to meet timing. simont 7781d 03h /
114 remove t2mod register simont 7784d 06h /
113 signal prsc_ow added. simont 7784d 06h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.