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Rev Log message Author Age Path
144 chsnge comp.des to des1 simont 7730d 18h /
143 add wire sub_result, conect it to des_acc and des1. simont 7730d 19h /
142 optimize state machine. simont 7731d 20h /
141 remove define OC8051_AS2_PCL, chane signal src_sel2 to 2 bit wide. simont 7731d 21h /
140 cahnge assigment to pc_wait (remove istb_o) simont 7731d 21h /
139 add aditional alu destination to solve critical path. simont 7732d 15h /
138 Change buffering to save one clock per instruction. simont 7732d 15h /
137 change to fit xrom. simont 7732d 20h /
136 registering outputs. simont 7732d 20h /
135 prepared start of receiving if ren is not active. simont 7738d 20h /
134 fix bug in case execution of two data dependent instructions. simont 7738d 20h /
133 fix bug in substraction. simont 7738d 22h /
132 change branch instruction execution (reduse needed clock periods). simont 7742d 14h /
131 prepare programs for new timing. simont 7742d 14h /
130 prepared programs for new timing. simont 7742d 14h /
129 updated... simont 7742d 14h /
128 chance idat_ir to 24 bit wide simont 7751d 21h /
127 fix bug (cyc_o and stb_o) simont 7751d 21h /
126 define OC8051_XILINX_RAMB added simont 7751d 21h /
125 update, add prescaler, rclk, tclk. simont 7751d 21h /

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