URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] - Rev 26

Rev	Log message	Author	Age	Path
26	main divider logic was optimized not optimized by compiler, so I did it by hand	markom	8019d 11h	/
25	divider and multiplier pass test	markom	8020d 05h	/
24	intensively tests all instructions	markom	8020d 10h	/
23	mul & div use 4 clocks	simont	8021d 01h	/
22	fix some bugs	simont	8021d 01h	/
21	mul bug fixed	markom	8021d 06h	/
20	multiplier and divider changed so they complete in 4 cycles	markom	8021d 08h	/
19	combinatorial loop removed	simont	8022d 01h	/
18	rst signal added	simont	8025d 06h	/
17	fix some bugs	simont	8025d 06h	/
16	inputs ram and op2 removed	simont	8025d 06h	/
15	commbinatorial loop removed	simont	8025d 06h	/
14	added signal ea_int	simont	8025d 08h	/
13	some bug fix	simont	8026d 04h	/
12	des1_r in alu port list	simont	8026d 04h	/
11	des2_r removed	simont	8026d 05h	/
10	% replaced with ^ in uart; some minor improvements	markom	8026d 11h	/
9	removed unused compare states	markom	8028d 03h	/
8	some IDS optimizations	markom	8028d 04h	/
7	immediate1 & immediate2 registers moved to oc8051_immediate_sel	markom	8028d 05h	/