URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] - Rev 30

Rev	Log message	Author	Age	Path
30	mode 1 and 3 divide clooak with 31 or 16, mode 2 with 64 or 32	simont	8019d 07h	/
29	fix some bugs	simont	8019d 08h	/
28	remove syn signal	simont	8019d 08h	/
27	fix some bugs	simont	8019d 09h	/
26	main divider logic was optimized not optimized by compiler, so I did it by hand	markom	8019d 10h	/
25	divider and multiplier pass test	markom	8020d 05h	/
24	intensively tests all instructions	markom	8020d 10h	/
23	mul & div use 4 clocks	simont	8021d 00h	/
22	fix some bugs	simont	8021d 00h	/
21	mul bug fixed	markom	8021d 06h	/
20	multiplier and divider changed so they complete in 4 cycles	markom	8021d 08h	/
19	combinatorial loop removed	simont	8022d 00h	/
18	rst signal added	simont	8025d 06h	/
17	fix some bugs	simont	8025d 06h	/
16	inputs ram and op2 removed	simont	8025d 06h	/
15	commbinatorial loop removed	simont	8025d 06h	/
14	added signal ea_int	simont	8025d 07h	/
13	some bug fix	simont	8026d 04h	/
12	des1_r in alu port list	simont	8026d 04h	/
11	des2_r removed	simont	8026d 04h	/