URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] - Rev 98

Rev	Log message	Author	Age	Path
98	move to rtl/verilog	simont	7797d 15h	/
97	initial inport	simont	7797d 15h	/
96	initial import	simont	7797d 15h	/
95	updating...	simont	7797d 16h	/
94	fix bug.	simont	7797d 16h	/
93	OC8051_XILINX_RAM added	simont	7797d 16h	/
92	initial inport	simont	7797d 16h	/
91	* empty log message *	simont	7797d 16h	/
90	change module name.	simont	7802d 09h	/
89	Replaced oc8051_ram by generic_dpram.	rherveille	7863d 13h	/
88	fix bugs	simont	7868d 13h	/
87	add include oc8051_defines.v	simont	7868d 13h	/
86	initial input	simont	7868d 13h	/
85	prepare bugs	simont	7868d 13h	/
84	remove wb_bus_mon	simont	7876d 12h	/
83	replace some modules	simont	7876d 13h	/
82	replace some modules	simont	7876d 13h	/
81	initial import	simont	7876d 13h	/
80	removing unused modules	simont	7876d 13h	/
79	initial import	simont	7876d 13h	/