OpenCores
URL https://opencores.org/ocsvn/RISCMCU/RISCMCU/trunk

Subversion Repositories RISCMCU

[/] - Rev 24

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
24 refer to counter.asm and counter.lst in the asm directory yapzihe 7992d 09h /
23 A demo of MAX+plus II .scf simulation file
The waveform shows how the MCU output 3, 2 and 1 to port B, port C and port D using different instructions.
yapzihe 7992d 09h /
22 hex2mif readme file yapzihe 7992d 09h /
21 hex2mif executable for windows yapzihe 7992d 09h /
20 a simple demo program that output 3, 2, 1 to port b, c and d with different way. yapzihe 7992d 09h /
19 1. Remove the use of frequency divider
2. Uses the same external interrupt pin and timer external clock source pin as AT90S1200
3. Adds some comments to each module instantation.
yapzihe 7994d 06h /
18 no message yapzihe 8000d 22h /
17 RISCMCU Slides Presentation (PDF, 112 KB) yapzihe 8006d 14h /
16 RISCMCU Thesis (PDF, 669 KB) yapzihe 8006d 14h /
15 rename file to RISCMCU_Thesis.pdf yapzihe 8006d 14h /
14 Thesis (PDF 668KB) yapzihe 8007d 02h /
13 removed old version yapzihe 8007d 02h /
12 RISCMCU THESIS (PDF, 668KB) yapzihe 8007d 02h /
11 My thesis for the RISCMCU project, in PDF yapzihe 8009d 07h /
10 hex2mif is used to convert HEX file to MIF format yapzihe 8009d 07h /
9 Real applications for testing the microcontroller yapzihe 8009d 07h /
8 move all the VHDL files to here from 'RISCMCU' directory yapzihe 8009d 07h /
7 move to 'vhdl' directory yapzihe 8009d 07h /
6 This commit was manufactured by cvs2svn to create tag 'arelease'. 8026d 01h /
5 no message yapzihe 8026d 01h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.