URL https://opencores.org/ocsvn/ae18/ae18/trunk

Subversion Repositories ae18

[/] - Rev 17

Rev	Log message	Author	Age	Path
17	Moved testbench into sim/verilog/testbench.v Minor cleanup.	sybreon	6291d 10h	/
16	Minor bug that causes the test to pass.	sybreon	6301d 08h	/
15	Fixed various bugs: - STATUS,C not correct for subtraction instructions - Data memory indirect addressing mode bugs - Other minor fixes	sybreon	6301d 10h	/
14	Minor simulation changes.	sybreon	6301d 10h	/
13	Compiles C test code using SDCC.	sybreon	6301d 10h	/
12	Rearranged code to make it synthesisable.	sybreon	6331d 09h	/
11	Minor bug fixes	sybreon	6396d 13h	/
10	Minor code clean up	sybreon	6396d 14h	/
9	Minor clean up	sybreon	6396d 14h	/
8	* empty log message *	sybreon	6396d 14h	/
7	added $Log$	sybreon	6396d 14h	/
6	* empty log message *	sybreon	6396d 14h	/
5	Added PCL read/write test	sybreon	6396d 14h	/
4	Minor bug fix for PCL read/write	sybreon	6396d 14h	/
3	Minor bug fix.	sybreon	6397d 00h	/
2	initial checkin	sybreon	6397d 17h	/
1	Standard project directories initialized by cvs2svn.		6397d 17h	/