URL https://opencores.org/ocsvn/aemb/aemb/trunk

Subversion Repositories aemb

[/] - Rev 19

Rev	Log message	Author	Age	Path
19	Added initial unified memory core.	sybreon	6393d 15h	/
18	Moved testbench into /sim/verilog. Simulation cleanups.	sybreon	6394d 07h	/
17	Cosmetic changes	sybreon	6395d 11h	/
16	Added pipeline stalling from incomplete bus cycles. Separated sync and async portions of code.	sybreon	6395d 23h	/
15	Removed ROM file. Please generate it from the SW directory.	sybreon	6402d 13h	/
14	Added initial interrupt/exception support.	sybreon	6402d 13h	/
13	Fibonacci rom	sybreon	6402d 21h	/
12	Minor changes	sybreon	6402d 21h	/
11	Removed unused signals	sybreon	6402d 21h	/
10	Fixed minor bugs	sybreon	6402d 21h	/
9	Extended testbench code	sybreon	6402d 21h	/
8	Fixed memory read-write data hazard	sybreon	6402d 21h	/
7	Added CMP instruction	sybreon	6402d 21h	/
6	Fixed C code bug which passes the test	sybreon	6402d 21h	/
5	Fixed endian correction issues on data bus.	sybreon	6403d 13h	/
4	Fixed a minor bug where RD is trashed by a STORE instruction. Spotted by Joon Lee.	sybreon	6411d 15h	/
3	initial import	sybreon	6428d 10h	/
2	initial import	sybreon	6428d 10h	/
1	Standard project directories initialized by cvs2svn.		6428d 10h	/