URL https://opencores.org/ocsvn/amber/amber/trunk

Subversion Repositories amber

[/] - Rev 46

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
46	svn ignore vmlinux.dis and vmlinux.mem	csantifort	4771d 10h	/
45	Store vmlinux.mem and vmlinux.dis in compressed form	csantifort	4771d 10h	/
44	Updated vmlinux image based on last change	csantifort	4771d 10h	/
43	Added support for the flat executable file format to vmlinux, so that the hello-world program is correctly relocated when it is loaded at the end of the vmlinux test. Changed the Virtex-5 clock configuration to use a 1200MHz VCO frequency and 80MHz system clock frequency.	csantifort	4771d 10h	/
42	Added write buffer - fixes bug if wishbone writes takes multiple cycles to complete	csantifort	4789d 07h	/
41	Added instructions on how to use Coregen to create the Spartan-6 DDR3 memory interface.	csantifort	4790d 15h	/
40	Added wishbone bus jitter testing option. Cleaned up waveform log .do files, now seperate files for a23 and a25 cores. Added vmlinux executable elf file for running on hardware.	csantifort	4795d 08h	/
39	Added a second level of buffering to a25_wishbone_buf to fix a lockup bug when write acks to not return immediately, and also to improve performance slightly	csantifort	4796d 09h	/
38	support 128-bit wishbone now used for a25 core	csantifort	4797d 08h	/
37	128-bit wide boot memory module	csantifort	4798d 07h	/
36	Changed boot_mem for the a25 system to be 128 bits wide to match the 128-bit wide wishbone bus	csantifort	4798d 08h	/
35	Amber25 improvements: Use 128-bit wishbone bus, instead of 32-bit to reduce cache miss fetch times Use a fast barrel shifter for shifts between 0 and 4 to improve timing Use a 2 cycle full barrel shifter for complex shifts	csantifort	4799d 15h	/
34	Tweaked strcpy function to speed it up slightly	csantifort	4800d 12h	/
33	Fixed bug in div assembly function. Handles negative numbers correctly. Fixed bug in printf function, negative numbers now print correctly.	csantifort	4801d 08h	/
32	Added clock cycle counting register to test_module to support dhrystone performance measurement	csantifort	4802d 08h	/
31	Added dhrystone benchmark test	csantifort	4802d 09h	/
30	Bug fix - a write access was sometimes dropped when it was in a sequence of writes with variable wb_ack delays	csantifort	4815d 15h	/
29	Use lgo command for saving waveforms in modelsim	csantifort	4817d 08h	/
28	Moved function prototypes to .h file	csantifort	4817d 09h	/
27	Got working with cadence nc simulator	csantifort	4850d 16h	/

1 2 Next >

Show All

Browse

Tools

Subversion Repositories amber

[/] - Rev 46

Filtering Options