OpenCores
URL https://opencores.org/ocsvn/amber/amber/trunk

Subversion Repositories amber

[/] - Rev 60

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
60 Bug fix; removed a combinational loop from the a25_decode logic. csantifort 4613d 17h /
59 Added modelsim script for reloading a wlf file after a simulation has been rerun. csantifort 4683d 14h /
58 Use TB.clk_count for the decompiler messages and removed the local counter csantifort 4683d 18h /
57 Add some debug messages csantifort 4683d 18h /
56 Remove the timeouts file from svn. Its an output file and gets now just gets created automatically
when sims are run for the first time.		 csantifort 4683d 18h /
55 Added sudo to rm mnt command csantifort 4683d 18h /
54 Bug fix for bug reported by Botao Lee. The mode bits in the decode stage did not change immediately
after a mode switch from a teqp instruction, but 1 cycle later. This meant the wrong set of registers
was selected for writing to for 1 clock cycle.		 csantifort 4700d 17h /
53 Cleaned up Amber Verilog, removing unused signals. csantifort 4715d 15h /
52 Fixed typo in notes on creating DDR memory interfaces using coregen csantifort 4715d 15h /
51 Revert vmlinux back to 48. csantifort 4756d 15h /
50 Revert to previous version csantifort 4756d 15h /
49 Added a note n how to change timeouts csantifort 4756d 15h /
48 Fixed a bug in linux that caused the os to not return to the running application after an interrupt.
Hello-world now runs stand-alone again.
Added initrd-200k-dhry, a disk image that uses the dhry program for init.		 csantifort 4760d 22h /
47 Changed V6 VCo from 1000Mhz to 1200 MHz csantifort 4780d 19h /
46 svn ignore vmlinux.dis and vmlinux.mem csantifort 4788d 17h /
45 Store vmlinux.mem and vmlinux.dis in compressed form csantifort 4788d 17h /
44 Updated vmlinux image based on last change csantifort 4788d 17h /
43 Added support for the flat executable file format to vmlinux, so that the hello-world program is correctly relocated when it is loaded at the end of the vmlinux test.
Changed the Virtex-5 clock configuration to use a 1200MHz VCO frequency and 80MHz system clock frequency.		 csantifort 4788d 17h /
42 Added write buffer - fixes bug if wishbone writes takes multiple cycles to complete csantifort 4806d 14h /
41 Added instructions on how to use Coregen to create the Spartan-6 DDR3 memory interface. csantifort 4807d 22h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.