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Rev Log message Author Age Path
68 Remove modelsim files. Only supporting Xilinx isim now. csantifort 4053d 10h /
67 renamed boot-loader.c to boot-loader-serial.c csantifort 4053d 10h /
66 Remove the stand-alone ethmac test. Use boot-loader-ethmac instead to verify ethmac functionality. csantifort 4053d 10h /
65 Renamed boot-loader to boot-loader-serial csantifort 4053d 10h /
64 Support latest Xilinx ISE 14.5 software. csantifort 4053d 11h /
63 Add support for Xilinx ISim Verilog simulator.
Remove Virtex-6 files.		 csantifort 4053d 15h /
62 Added source for amber-pkt2mem csantifort 4206d 04h /
61 Add new netowkr based boot loader.
Remove support for Virtex. Spartan 6 only now.		 csantifort 4340d 09h /
60 Bug fix; removed a combinational loop from the a25_decode logic. csantifort 4558d 06h /
59 Added modelsim script for reloading a wlf file after a simulation has been rerun. csantifort 4628d 03h /
58 Use TB.clk_count for the decompiler messages and removed the local counter csantifort 4628d 07h /
57 Add some debug messages csantifort 4628d 07h /
56 Remove the timeouts file from svn. Its an output file and gets now just gets created automatically
when sims are run for the first time.		 csantifort 4628d 07h /
55 Added sudo to rm mnt command csantifort 4628d 07h /
54 Bug fix for bug reported by Botao Lee. The mode bits in the decode stage did not change immediately
after a mode switch from a teqp instruction, but 1 cycle later. This meant the wrong set of registers
was selected for writing to for 1 clock cycle.		 csantifort 4645d 06h /
53 Cleaned up Amber Verilog, removing unused signals. csantifort 4660d 04h /
52 Fixed typo in notes on creating DDR memory interfaces using coregen csantifort 4660d 04h /
51 Revert vmlinux back to 48. csantifort 4701d 04h /
50 Revert to previous version csantifort 4701d 04h /
49 Added a note n how to change timeouts csantifort 4701d 04h /

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