URL https://opencores.org/ocsvn/amber/amber/trunk

Subversion Repositories amber

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Rev	Log message	Author	Age	Path
71	Original Amber 23 core uses asyncronous implementation of register bank. It leads to some problems with ram-based implementation of the register bank, because at least Altera FPGAs uses syncronous ram blocks, so the whole address needs to be latched. The patch exposes non-registered versions of register select signals to the register bank, so the bank can build address and latch it in the syncronous ram input register. The patch is a pre-requisite for ram-based register bank implementation on Altera FPGA. Contributed by Dmitry Tarnyagin <dmitry.tarnyagin@lockless.no>	csantifort	4056d 11h	/
70	The mlas_bug testcase tried to use stack without setting stack pointer register, causing unpredictable behavoiur. The patch uses an expilict stack area for the test. Contributed by: Dmitry Tarnyagin <dmitry.tarnyagin@lockless.no>	csantifort	4056d 11h	/
69	Updated the spec for ISE 14.5, boot-loader-ethmac.	csantifort	4056d 11h	/
68	Remove modelsim files. Only supporting Xilinx isim now.	csantifort	4056d 12h	/
67	renamed boot-loader.c to boot-loader-serial.c	csantifort	4056d 12h	/
66	Remove the stand-alone ethmac test. Use boot-loader-ethmac instead to verify ethmac functionality.	csantifort	4056d 12h	/
65	Renamed boot-loader to boot-loader-serial	csantifort	4056d 12h	/
64	Support latest Xilinx ISE 14.5 software.	csantifort	4056d 12h	/
63	Add support for Xilinx ISim Verilog simulator. Remove Virtex-6 files.	csantifort	4056d 17h	/
62	Added source for amber-pkt2mem	csantifort	4209d 05h	/
61	Add new netowkr based boot loader. Remove support for Virtex. Spartan 6 only now.	csantifort	4343d 11h	/
60	Bug fix; removed a combinational loop from the a25_decode logic.	csantifort	4561d 07h	/
59	Added modelsim script for reloading a wlf file after a simulation has been rerun.	csantifort	4631d 05h	/
58	Use TB.clk_count for the decompiler messages and removed the local counter	csantifort	4631d 08h	/
57	Add some debug messages	csantifort	4631d 08h	/
56	Remove the timeouts file from svn. Its an output file and gets now just gets created automatically when sims are run for the first time.	csantifort	4631d 08h	/
55	Added sudo to rm mnt command	csantifort	4631d 09h	/
54	Bug fix for bug reported by Botao Lee. The mode bits in the decode stage did not change immediately after a mode switch from a teqp instruction, but 1 cycle later. This meant the wrong set of registers was selected for writing to for 1 clock cycle.	csantifort	4648d 08h	/
53	Cleaned up Amber Verilog, removing unused signals.	csantifort	4663d 06h	/
52	Fixed typo in notes on creating DDR memory interfaces using coregen	csantifort	4663d 06h	/

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Subversion Repositories amber

[/] - Rev 71

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