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Rev Log message Author Age Path
12 added PSELx on WR_ENA, RD_ENA to correct read/write when PSEL is HIGH redbear 3751d 06h /
11 Added configuration to define RX and TX operation and configure propely the ports. redbear 3758d 03h /
10 Correcting a few words wrote wrong. redbear 3758d 03h /
9 More description added on spec redbear 3759d 04h /
8 More description added on spec redbear 3759d 04h /
7 Corrected CLOCK generated by SCL according NXP spec. redbear 3760d 05h /
6 Adding a basic FSM to RX. redbear 3765d 06h /
5 Added about APB address necessary to read and write on FIFOS and register configuration. redbear 3773d 03h /
4 Added on module I2C basic error for register configuration redbear 3773d 05h /
3 Added a basic example on I2C Block. redbear 3773d 05h /
2 Adding files and initial version. redbear 3774d 01h /
1 The project and the structure was created root 3777d 01h /

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