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Rev Log message Author Age Path
17 fifo.v and dual_port_ram.v celaya.dario 3749d 04h /
16 fifo.v and dual_port_ram.v celaya.dario 3749d 04h /
15 11'd1 to 4'd1 redbear 3755d 10h /
14 added a and to make real full fifo. redbear 3755d 10h /
13 re write all fifo module to write and give full when the same is not full redbear 3755d 10h /
12 added PSELx on WR_ENA, RD_ENA to correct read/write when PSEL is HIGH redbear 3755d 10h /
11 Added configuration to define RX and TX operation and configure propely the ports. redbear 3762d 06h /
10 Correcting a few words wrote wrong. redbear 3762d 07h /
9 More description added on spec redbear 3763d 08h /
8 More description added on spec redbear 3763d 08h /
7 Corrected CLOCK generated by SCL according NXP spec. redbear 3764d 09h /
6 Adding a basic FSM to RX. redbear 3769d 09h /
5 Added about APB address necessary to read and write on FIFOS and register configuration. redbear 3777d 06h /
4 Added on module I2C basic error for register configuration redbear 3777d 09h /
3 Added a basic example on I2C Block. redbear 3777d 09h /
2 Adding files and initial version. redbear 3778d 05h /
1 The project and the structure was created root 3781d 05h /

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