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Rev Log message Author Age Path
20 Finished a previous version from RX and added SDA and SCL enable to PADS. redbear 3685d 05h /
19 changes about area use for proprely use. redbear 3730d 04h /
18 Corrected fifo mem acess, i2c_module and revised conections on top redbear 3747d 05h /
17 fifo.v and dual_port_ram.v celaya.dario 3748d 05h /
16 fifo.v and dual_port_ram.v celaya.dario 3748d 05h /
15 11'd1 to 4'd1 redbear 3754d 11h /
14 added a and to make real full fifo. redbear 3754d 11h /
13 re write all fifo module to write and give full when the same is not full redbear 3754d 11h /
12 added PSELx on WR_ENA, RD_ENA to correct read/write when PSEL is HIGH redbear 3754d 11h /
11 Added configuration to define RX and TX operation and configure propely the ports. redbear 3761d 07h /
10 Correcting a few words wrote wrong. redbear 3761d 07h /
9 More description added on spec redbear 3762d 09h /
8 More description added on spec redbear 3762d 09h /
7 Corrected CLOCK generated by SCL according NXP spec. redbear 3763d 10h /
6 Adding a basic FSM to RX. redbear 3768d 10h /
5 Added about APB address necessary to read and write on FIFOS and register configuration. redbear 3776d 07h /
4 Added on module I2C basic error for register configuration redbear 3776d 10h /
3 Added a basic example on I2C Block. redbear 3776d 10h /
2 Adding files and initial version. redbear 3777d 06h /
1 The project and the structure was created root 3780d 06h /

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