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Rev Log message Author Age Path
77 pass syn elaboration wsong0210 4713d 03h /
76 fix syntex wsong0210 4717d 03h /
75 code finished, start the debugging wsong0210 4717d 03h /
74 in/out buffer finished wsong0210 4718d 03h /
73 input buffer wsong0210 4725d 02h /
72 clos-opt ongoing, Clos switch finished, nxt input buffer wsong0210 4726d 03h /
71 the buffered 2-stage Clos switch wsong0210 4727d 03h /
70 clos-opt ongoing wsong0210 4727d 03h /
69 central module of the Clos wsong0210 4730d 03h /
68 rewite the clos switch in the SDM-Clos-buf router wsong0210 4731d 03h /
67 structure not good, prepare to use new files wsong0210 4731d 04h /
66 clos opt ongoing wsong0210 4745d 21h /
65 pipeline controller wsong0210 4745d 21h /
64 clos opt ongoing wsong0210 4745d 21h /
63 clos opt ongoing wsong0210 4746d 02h /
62 clos opt ongoing wsong0210 4747d 03h /
61 settle down the pipeline controller wsong0210 4752d 02h /
60 try to make the address comparison relaxed QDI wsong0210 4755d 03h /
59 address deduction wsong0210 4757d 02h /
58 opt ongoing 10/06/2011 wsong0210 4758d 03h /

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