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Rev Log message Author Age Path
12 Fixed some blocking versus non-blocking statement issues. rherveille 8369d 21h /
11 Created directory structure (documentation, vhdl, verilog) rherveille 8380d 10h /
10 - renamed 'ata.vhd' to 'atahost.vhd'
- Changed 'go' & 'igo' generation (pio_tctrl.vhdl).
rherveille 8385d 11h /
9 - renamed 'ata.vhd' to 'atahost.vhd'
- Changed PIOreq & PIOack generation (controller.vhd); made them synchronous
- Changed 'go' & 'igo' generation (pio_tctrl.vhdl).
rherveille 8385d 11h /
8 Fixed sensitivity error in ata.v (nRESET instead of nReset) rherveille 8385d 21h /
7 no message rherveille 8387d 08h /
6 Added 'timescale to all files
Fixed bug where control registers would always latch data, instead of when addressed
rherveille 8387d 08h /
5 Rewrote some sections. Minor Verilog coding style issues. rherveille 8393d 13h /
4 Fixed some incomplete port lists. Fixed some Verilog related issues.
Design now compiles completely.
rherveille 8394d 18h /
3 Created VHDL & Verilog subdirectories. Moved files accordingly. rherveille 8397d 13h /
2 Initial verilog release rherveille 8397d 13h /
1 Standard project directories initialized by cvs2svn. 8397d 13h /

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