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Rev	Log message	Author	Age	Path
20	Some minor bug fixes	rherveille	8411d 04h	/
19	Changed RST_LVL define to parameter. Removed atahost_define.v	rherveille	8420d 10h	/
18	Changed dd_padoen_o portname into dd_pad_oe_o, because it is active high.	rherveille	8448d 13h	/
17	Changed top-level. Made asynchronous reset programmable.	rherveille	8454d 10h	/
16	- Added Test Bench - Added Synthesis scripts for Design Compiler - Fixed minor bug in atahost_top	rudi	8481d 09h	/
15	Changed filenames and top-level port names to be conform new OpenCores conventions	rherveille	8482d 07h	/
14	created new directory structure	rherveille	8494d 08h	/
13	no message	rherveille	8494d 08h	/
12	Fixed some blocking versus non-blocking statement issues.	rherveille	8501d 13h	/
11	Created directory structure (documentation, vhdl, verilog)	rherveille	8512d 02h	/
10	- renamed 'ata.vhd' to 'atahost.vhd' - Changed 'go' & 'igo' generation (pio_tctrl.vhdl).	rherveille	8517d 03h	/
9	- renamed 'ata.vhd' to 'atahost.vhd' - Changed PIOreq & PIOack generation (controller.vhd); made them synchronous - Changed 'go' & 'igo' generation (pio_tctrl.vhdl).	rherveille	8517d 03h	/
8	Fixed sensitivity error in ata.v (nRESET instead of nReset)	rherveille	8517d 13h	/
7	no message	rherveille	8519d 00h	/
6	Added 'timescale to all files Fixed bug where control registers would always latch data, instead of when addressed	rherveille	8519d 00h	/
5	Rewrote some sections. Minor Verilog coding style issues.	rherveille	8525d 05h	/
4	Fixed some incomplete port lists. Fixed some Verilog related issues. Design now compiles completely.	rherveille	8526d 10h	/
3	Created VHDL & Verilog subdirectories. Moved files accordingly.	rherveille	8529d 05h	/
2	Initial verilog release	rherveille	8529d 05h	/
1	Standard project directories initialized by cvs2svn.		8529d 05h	/

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[/] - Rev 20

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