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Rev Log message Author Age Path
22 Added disclaimer
Added CVS information
Changed core for new internal counter libraries (synthesis fixes).
rherveille 8155d 02h /
21 Changed atahost_top pin-information. rherveille 8155d 02h /
20 Some minor bug fixes rherveille 8268d 21h /
19 Changed RST_LVL define to parameter.
Removed atahost_define.v
rherveille 8278d 03h /
18 Changed dd_padoen_o portname into dd_pad_oe_o, because it is active high. rherveille 8306d 07h /
17 Changed top-level. Made asynchronous reset programmable. rherveille 8312d 04h /
16 - Added Test Bench
- Added Synthesis scripts for Design Compiler
- Fixed minor bug in atahost_top
rudi 8339d 02h /
15 Changed filenames and top-level port names to be conform new OpenCores conventions rherveille 8340d 01h /
14 created new directory structure rherveille 8352d 02h /
13 no message rherveille 8352d 02h /
12 Fixed some blocking versus non-blocking statement issues. rherveille 8359d 07h /
11 Created directory structure (documentation, vhdl, verilog) rherveille 8369d 19h /
10 - renamed 'ata.vhd' to 'atahost.vhd'
- Changed 'go' & 'igo' generation (pio_tctrl.vhdl).
rherveille 8374d 21h /
9 - renamed 'ata.vhd' to 'atahost.vhd'
- Changed PIOreq & PIOack generation (controller.vhd); made them synchronous
- Changed 'go' & 'igo' generation (pio_tctrl.vhdl).
rherveille 8374d 21h /
8 Fixed sensitivity error in ata.v (nRESET instead of nReset) rherveille 8375d 07h /
7 no message rherveille 8376d 17h /
6 Added 'timescale to all files
Fixed bug where control registers would always latch data, instead of when addressed
rherveille 8376d 17h /
5 Rewrote some sections. Minor Verilog coding style issues. rherveille 8382d 22h /
4 Fixed some incomplete port lists. Fixed some Verilog related issues.
Design now compiles completely.
rherveille 8384d 03h /
3 Created VHDL & Verilog subdirectories. Moved files accordingly. rherveille 8386d 22h /

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