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Rev	Log message	Author	Age	Path
23	Moved wishbone interface into 'atahost_wb_slave.v' Major revisions in all cores.	rherveille	8145d 16h	/
22	Added disclaimer Added CVS information Changed core for new internal counter libraries (synthesis fixes).	rherveille	8147d 20h	/
21	Changed atahost_top pin-information.	rherveille	8147d 20h	/
20	Some minor bug fixes	rherveille	8261d 16h	/
19	Changed RST_LVL define to parameter. Removed atahost_define.v	rherveille	8270d 22h	/
18	Changed dd_padoen_o portname into dd_pad_oe_o, because it is active high.	rherveille	8299d 01h	/
17	Changed top-level. Made asynchronous reset programmable.	rherveille	8304d 22h	/
16	- Added Test Bench - Added Synthesis scripts for Design Compiler - Fixed minor bug in atahost_top	rudi	8331d 21h	/
15	Changed filenames and top-level port names to be conform new OpenCores conventions	rherveille	8332d 19h	/
14	created new directory structure	rherveille	8344d 20h	/
13	no message	rherveille	8344d 20h	/
12	Fixed some blocking versus non-blocking statement issues.	rherveille	8352d 01h	/
11	Created directory structure (documentation, vhdl, verilog)	rherveille	8362d 14h	/
10	- renamed 'ata.vhd' to 'atahost.vhd' - Changed 'go' & 'igo' generation (pio_tctrl.vhdl).	rherveille	8367d 15h	/
9	- renamed 'ata.vhd' to 'atahost.vhd' - Changed PIOreq & PIOack generation (controller.vhd); made them synchronous - Changed 'go' & 'igo' generation (pio_tctrl.vhdl).	rherveille	8367d 15h	/
8	Fixed sensitivity error in ata.v (nRESET instead of nReset)	rherveille	8368d 01h	/
7	no message	rherveille	8369d 12h	/
6	Added 'timescale to all files Fixed bug where control registers would always latch data, instead of when addressed	rherveille	8369d 12h	/
5	Rewrote some sections. Minor Verilog coding style issues.	rherveille	8375d 17h	/
4	Fixed some incomplete port lists. Fixed some Verilog related issues. Design now compiles completely.	rherveille	8376d 22h	/

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[/] - Rev 23

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