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Rev	Log message	Author	Age	Path
24	Initial Verilog HDL release	rherveille	8139d 03h	/
23	Moved wishbone interface into 'atahost_wb_slave.v' Major revisions in all cores.	rherveille	8139d 03h	/
22	Added disclaimer Added CVS information Changed core for new internal counter libraries (synthesis fixes).	rherveille	8141d 06h	/
21	Changed atahost_top pin-information.	rherveille	8141d 06h	/
20	Some minor bug fixes	rherveille	8255d 02h	/
19	Changed RST_LVL define to parameter. Removed atahost_define.v	rherveille	8264d 08h	/
18	Changed dd_padoen_o portname into dd_pad_oe_o, because it is active high.	rherveille	8292d 11h	/
17	Changed top-level. Made asynchronous reset programmable.	rherveille	8298d 08h	/
16	- Added Test Bench - Added Synthesis scripts for Design Compiler - Fixed minor bug in atahost_top	rudi	8325d 07h	/
15	Changed filenames and top-level port names to be conform new OpenCores conventions	rherveille	8326d 05h	/
14	created new directory structure	rherveille	8338d 07h	/
13	no message	rherveille	8338d 07h	/
12	Fixed some blocking versus non-blocking statement issues.	rherveille	8345d 12h	/
11	Created directory structure (documentation, vhdl, verilog)	rherveille	8356d 00h	/
10	- renamed 'ata.vhd' to 'atahost.vhd' - Changed 'go' & 'igo' generation (pio_tctrl.vhdl).	rherveille	8361d 02h	/
9	- renamed 'ata.vhd' to 'atahost.vhd' - Changed PIOreq & PIOack generation (controller.vhd); made them synchronous - Changed 'go' & 'igo' generation (pio_tctrl.vhdl).	rherveille	8361d 02h	/
8	Fixed sensitivity error in ata.v (nRESET instead of nReset)	rherveille	8361d 12h	/
7	no message	rherveille	8362d 22h	/
6	Added 'timescale to all files Fixed bug where control registers would always latch data, instead of when addressed	rherveille	8362d 22h	/
5	Rewrote some sections. Minor Verilog coding style issues.	rherveille	8369d 03h	/

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[/] - Rev 24

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