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Rev	Log message	Author	Age	Path
25	renamed 'atahost.vhd' to 'atahost_top.vhd' renamed 'controller.vhd' to 'atahost_controller.vhd' renamed 'pio_tctrl.vhd' to 'atahost_pio_tctrl.vhd' broke-up 'counter.vhd' into 'ud_cnt.vhd' and 'ro_cnt.vhd' changed resD input to generic RESD in ud_cnt.vhd changed ID input to generic ID in ro_cnt.vhd changed core to reflect changes in ro_cnt.vhd removed references to 'count' library changed IO names added disclaimer added CVS log moved registers and wishbone signals into 'atahost_wb_slave.vhd' core is now equivalent to verilog version	rherveille	8161d 20h	/
24	Initial Verilog HDL release	rherveille	8161d 20h	/
23	Moved wishbone interface into 'atahost_wb_slave.v' Major revisions in all cores.	rherveille	8161d 20h	/
22	Added disclaimer Added CVS information Changed core for new internal counter libraries (synthesis fixes).	rherveille	8164d 00h	/
21	Changed atahost_top pin-information.	rherveille	8164d 00h	/
20	Some minor bug fixes	rherveille	8277d 20h	/
19	Changed RST_LVL define to parameter. Removed atahost_define.v	rherveille	8287d 01h	/
18	Changed dd_padoen_o portname into dd_pad_oe_o, because it is active high.	rherveille	8315d 05h	/
17	Changed top-level. Made asynchronous reset programmable.	rherveille	8321d 02h	/
16	- Added Test Bench - Added Synthesis scripts for Design Compiler - Fixed minor bug in atahost_top	rudi	8348d 00h	/
15	Changed filenames and top-level port names to be conform new OpenCores conventions	rherveille	8348d 23h	/
14	created new directory structure	rherveille	8361d 00h	/
13	no message	rherveille	8361d 00h	/
12	Fixed some blocking versus non-blocking statement issues.	rherveille	8368d 05h	/
11	Created directory structure (documentation, vhdl, verilog)	rherveille	8378d 17h	/
10	- renamed 'ata.vhd' to 'atahost.vhd' - Changed 'go' & 'igo' generation (pio_tctrl.vhdl).	rherveille	8383d 19h	/
9	- renamed 'ata.vhd' to 'atahost.vhd' - Changed PIOreq & PIOack generation (controller.vhd); made them synchronous - Changed 'go' & 'igo' generation (pio_tctrl.vhdl).	rherveille	8383d 19h	/
8	Fixed sensitivity error in ata.v (nRESET instead of nReset)	rherveille	8384d 05h	/
7	no message	rherveille	8385d 15h	/
6	Added 'timescale to all files Fixed bug where control registers would always latch data, instead of when addressed	rherveille	8385d 16h	/

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[/] - Rev 25

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