URL https://opencores.org/ocsvn/ata/ata/trunk

Subversion Repositories ata

[/] - Rev 6

Rev	Log message	Author	Age	Path
6	Added 'timescale to all files Fixed bug where control registers would always latch data, instead of when addressed	rherveille	8377d 11h	/
5	Rewrote some sections. Minor Verilog coding style issues.	rherveille	8383d 16h	/
4	Fixed some incomplete port lists. Fixed some Verilog related issues. Design now compiles completely.	rherveille	8384d 20h	/
3	Created VHDL & Verilog subdirectories. Moved files accordingly.	rherveille	8387d 15h	/
2	Initial verilog release	rherveille	8387d 15h	/
1	Standard project directories initialized by cvs2svn.		8387d 15h	/